This application relies for priority upon Korean Patent Application Nos. 99-39548 and 00-42153, filed on Sep. 15, 1999, and Jul. 22, 2000, respectively, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a method of forming a metal interconnection using plating and a semiconductor device manufactured by the method. More particularly, the present invention relates to a method for manufacturing a metal interconnection in a semiconductor device having a damascene structure and a semiconductor device manufactured by such a method.
In order to reduce RC delay time in a semiconductor device, a method has been studied of forming a metal interconnection layer using metal such as copper, which has a low resistivity. A reduction in RC delay time is particularly useful in logic devices that require a high operation speed.
In one method of forming a metal interconnection material, a metal interconnection material, such as aluminum, is formed over the entire surface of a substrate and the resultant structure is patterned by a conventional photolithography process. However, a different method is used when forming a metal interconnection layer with copper (Cu) as a metal interconnection material because it is difficult to perform a patterning process with respect to copper. In order to form a metal interconnection layer using this process, a region where a metal interconnection is to be made is formed in an insulation layer on a substrate in advance, and then this area is filled with a metal interconnection material. A so-called xe2x80x9cdamascenexe2x80x9d process is used to achieve this method.
FIGS. 1 through 3 are sectional views for explaining a method of forming a metal interconnection of a semiconductor device having a conventional line damascene structure. In the line damascene structure, a trench having a predetermined depth from the surface of an insulation layer is formed in a line and a metal interconnection layer is formed in the trench. A method of forming a metal interconnection of a line damascene structure will now be described with reference to the attached drawings.
Referring to FIG. 1, a trench region 11 of a line shape is formed by performing a photolithography process on an insulation layer 10, which is formed over a substrate 5. Subsequently, a diffusion prevention layer 12 is formed over the entire surface of the insulation layer 10, including the trench region 11. Next, copper is deposited over the diffusion prevention layer 12 by a physical vapor deposition (PVD) method such as sputtering, thereby forming a seed layer 14.
Referring to FIG. 2, a plating layer 16 of copper is then formed over the resultant structure, including the seed layer 14, using an electroplating method. The plating layer 16 is formed thick enough to completely fill the trench region 11.
Referring to FIG. 3, some of the plating layer 16 is then removed by a chemical-mechanical polishing (CMP) process until a portion of the insulation layer 10 is exposed. As a result of this, remaining portions of the diffusion prevention layer 12 and the seed layer 14, as well as a metal interconnection layer 16a that is formed from the portion of the plating layer 16 remains within each trench region 11, in the vicinity of the surface of the insulation layer 10.
FIGS. 4 through 7 are a plan view and section views for explaining a method of forming a metal interconnection of a semiconductor device having a conventional dual damascene structure. In the dual damascene structure, a metal interconnection formed to fill a trench region of a line shape is combined with a contact filling a contact hole or a via-hole in order to connect to an underlying conductive layer. A method of forming a metal interconnection of a dual damascene structure will be described below.
Referring to FIG. 4, lower conductive layers 28 are formed over a substrate 5 at a predetermined interval. Metal interconnection layers 26a are formed over the lower conductive layers 28 at another predetermined interval. An insulation layer (not shown in FIG. 4) is interposed between the metal interconnection layer 26a and the underlying lower conductive layer 28. The metal interconnection layer 26a is electrically connected to the underlying lower conductive layer 28 through a contact hole region 30. FIGS. 5 through 7 are sectional views of FIG. 4 taken along the line VII-VIIxe2x80x2, and show the sequential steps of fabricating the device of FIG. 4.
Referring to FIG. 5, a conductive material is deposited and patterned over a substrate 15 to form lower conductive layers 28 at regular intervals. Subsequently, an insulation layer 20 is formed over the entire surface of the resultant structure, including the lower conductive layers 28. A typical photolithography process is then performed on the insulation layer 20 to form a contact hole region 30 and a trench region 31 that includes the contact hole region 30. Next, a diffusion prevention layer 22 and a seed layer 24 are sequentially formed over the entire surface of the resultant structure, including the contact hole region 30 and the trench region 31.
Referring to FIG. 6, the substrate 15 over which the seed layer 24 is formed is then loaded into an electroplating apparatus and is electroplated to form a plating layer 26 of copper.
Referring to FIG. 7, the surface of the substrate 15, including the plating layer 26, is then planarized by a chemical mechanical polishing (CMP) process. This surface polarization is performed on the plating layer 26, the seed layer 24, and the diffusion prevention layer 22 until the surface of the insulation layer 20 is exposed. In this way a metal interconnection layer 26a is formed that has a dual damascene structure and a planarized surface, as shown in FIG. 7.
However, the method described above of forming a metal interconnection having a line or dual damascene structure has several problems. First, copper must be thickly deposited to make certain that enough copper is deposited to form a layer that fills the trench region 31 and has at least a predetermined thickness over the insulation layer 24, taking into account the depth of the trench region 31 and contact hole region 30, and the parameters of the chemical mechanical polishing (CMP) process. Thus, the amount of copper subject to the polishing is large. This decreases the throughput of the fabrication process decreases, and increases fabrication expense.
Second, as the amount of copper subject to the polishing increases, the uniformity of the chemical mechanical polishing (CMP) process is degraded. This causes the thickness of a metal interconnection layer 26a finally formed in a substrate 15 to vary according to its location, which directly affects the reliability and throughput of the devices.
Third, when removing the copper layer using the chemical mechanical polishing (CMP) process, corrosion of the insulation layer 24 occurs according to the density of a metal interconnection layer pattern. This also causes the thicknesses of the metal interconnection layers 26a in a substrate 15 to vary, which, as noted above, results in defects.
Fourth, different slurries must be used when polishing a seed layer 24 and a diffusion prevention layer 22 when the seed layer 24 and the diffusion prevention layer 22 have different polishing speeds. This complicates the chemical mechanical polishing (CMP) process and increases fabrication expense.
Fifth, in a dual damascene structure, the aspect ratio of a contact hole region 30 is very large, which may result in the formation of a void 32 during electroplating, as shown in FIG. 6. Such a void 32, as shown in FIG. 7, remains as a void defect 32a on the surface of the metal interconnection layer 26a after surface polarization, thereby deteriorating the reliability of the resulting devices.
It is a first objective of the present invention to provide a method of forming a metal interconnection using a plating process, which can improve the throughput and reliability of semiconductor devices by decreasing the required polishing in a chemical mechanical polishing (CMP) process.
It is a second objective of the present invention to provide a semiconductor device, which decreases the variation in the thicknesses of metal interconnection layers in a given substrate, and removes void defects, thereby improving the reliability of the device.
To achieve the first objective, the present invention provides a method of forming a metal interconnection. This method comprises forming an insulation region on a substrate; forming a recess region in the insulation layer; forming a diffusion prevention layer over insulation layer and the recess region; forming a metal seed layer over the diffusion prevention layer only in the recess region; and forming a conductive plating layer on the seed layer using plating process.
The recess region may comprise a trench region of a line shape having a predetermined depth from a top surface of the insulation layer. The recess region, may also comprise a trench region of a line shape having a predetermined depth from the surface of the insulation layer; and a contact hole region passing through the insulation layer.
Forming the metal seed layer may further comprise forming a preliminary seed layer over the diffusion prevention layer; and removing a first portion of the preliminary seed layer outside of the recess region such that a second portion of the preliminary seed layer in the recess region forms the metal seed layer. Forming the preliminary seed layer is preferably performed by a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method.
Removing a first portion of the preliminary seed layer is preferably performed by a chemical mechanical polishing (CMP) process. The slurry used for the chemical mechanical polishing (CMP) process preferably does not contain abrasives. The chemical-mechanical polishing (CMP) process preferably uses a slurry having a polishing selection ratio of 10:1-1000:1 with respect to the preliminary seed layer and the diffusion prevention layer.
Removing a first portion of the preliminary seed layer preferably leaves the second portion of the preliminary seed layer and a third portion of the preliminary seed layer in the recess region. In addition, the method may further comprise performing a wet etching process on the third portion of the preliminary seed layer to remove the third portion of the seed layer from the recess region. The wet etching process is preferably time-controlled.
The second portion of the preliminary seed layer is preferably formed only on a bottom surface of the recess region.
Removing a first portion of the preliminary seed layer may further comprise forming an intermediate material layer over the preliminary seed layer to fill the recess region; etching back and removing a first portion of the intermediate material layer and the first portion of the preliminary seed layer until a portion of the diffusion prevention layer outside the recess region is exposed; and removing a second portion of the intermediate material layer remaining in the recess region. The intermediate material layer preferably comprises a photoresist material.
The method may further comprise performing a surface polarization process on the conductive plating layer and the diffusion prevention layer to expose a top surface of the insulation layer and to form a metal interconnection layer in the recess region. The surface polarization is preferably performed by a chemical mechanical polishing process using a slurry having nearly the same polishing speeds with respect to the diffusion prevention layer and the plating layer.
To achieve the second objective, the present invention provides a semiconductor device including a substrate; an insulation layer formed over the substrate, the insulation layer having a recess region is formed in it; a diffusion prevention layer formed over the insulation layer and in the recess region; a metal seed layer formed over the diffusion prevention layer and in the recess region; and a metal interconnection layer formed in the recess region on the metal seed layer therein.
The recess region preferably comprises a trench region of a line shape having a predetermined depth from the surface of the insulation layer, and the metal seed layer is formed over a bottom portion of the trench region.
The semiconductor device may further comprising a lower conductive layer formed over the substrate. The recess region may comprises a contact hole region that passes through the insulation layer and exposes the lower conductive layer. In this case, the diffusion prevention layer is preferably formed in the contact hole region and over the lower conductive layer, and the metal seed layer is preferably formed over the bottom portion of the contact hole.
The recess region may further comprise a trench region of a line shape having a predetermined depth from the surface of the insulation layer. In this case, the metal seed layer is preferably formed over a bottom portion of the contact hole and a bottom portion of the trench region.
The diffusion prevention layer preferably comprises a material selected from the group consisting of a tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi2), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), cobalt (Co), cobalt silicide (CoSi2), and a composite layer comprising at least two of these materials. The metal seed layer preferably comprises a material selected from the transition metal group of copper, platinum, palladium, rubidium, strontium, rhodium, and cobalt. Preferably, the metal seed layer and the metal interconnection layer both comprise copper.
According to the present invention, the plating layer is formed only in the recess region in which the metal interconnection layer will be formed so that the plating layer does not have to be formed any thicker than needed, thus greatly reducing the amount of metal to be polished during a subsequent CMP process. This improves fabrication throughput and decreases fabrication expense.
In addition, since the amount of the plating layer to be polished by the polishing process is small, the uniformity of the CMP process in a given substrate is excellent, which decreases the variation in the thicknesses of the metal interconnection layers formed in the substrate. Moreover, this can prevent dishing or corrosion of the insulation layer because the polishing process does not need to be excessively performed.
Furthermore, the fabrication process is simplified by allowing the use of a slurry having nearly the same polishing speed with respect to the plating layer and the diffusion prevention layer when polishing the plating layer and the diffusion prevention layer.
Moreover, the seed layer on the sidewalls of the recess region is removed by a wet etching process, which decreases the aspect ratio of the recess region. This improves the gap-filling performance of the plating layer, thereby preventing void defects. Consequently, this improves the reliability of the resulting semiconductor devices.